Radiation events can cause spurious signals (i.e. transients) to be generated in logic gates that can in turn cause system-level malfunctions in high performance System-on-a-Chip (SoC) devices. As technologies scale down to tens of nanometers, it has become increasingly difficult to design transient-mitigated logic gates with minimal performance and power penalties. Of particular interest is the design of transient-mitigated logic gates for high fanout nets (e.g., clock and reset distribution networks) in high performance SoCs fabricated in modern bulk Fin Field Effect Transistor (FinFET) technologies (e.g., GlobalFoundries 14LPP bulk FinFET technology).
There are no known logic gate designs that fully mitigate for transients in modern bulk FinFET technologies with minimal power and performance penalties. Temporal filtering techniques may be used in addition to traditional logic gates to mitigate transients. However, the main drawback to filtering, especially on high-fanout high-activity nets, such as a clock, is the enormous increase in power consumption. Additionally, filtering consumes significantly more area in advanced technologies due to the fact that the logic gates with which the filters are built have reduced propagation delays, thereby resulting in more logic gates per filter. Filtering, or any temporal based mitigation technique, additionally requires extensive and costly characterization of each technology in order to determine how much filtering is needed.
In light of the foregoing, there is a need for an improved design for transient-mitigated logic gates to reduce SoC error rates to acceptable levels.